1. Field of the Invention
The present invention relates to digital phase lock loops and more specifically to digital phase lock loops used to filter jitter and frequency offset from a periodic input signal.
2. Background Art
Periodic signals transmitted on a transmission medium are often subject to jitter. Jitter occurs when a periodic signal centers about a certain phase orientation, but a given cycle of the periodic signal is prone to be slightly shined in phase from the center phase orientation. In other words, a given cycle may lead (i.e. occur earlier than) or lag (i.e. occur later the) a hypothetical signal which is exactly in phase with the center phase orientation.
Jitter itself is often a periodic phenomenon. Jitter, the amount of lead or lag (measured in units of time) on each successive cycle of a waveform, will often exhibit a waveform such as a sinusoidal waveform, a triangular waveform, etc. A periodic jitter waveform has a peak-to-peak amplitude which is the sum of the maximum lead and the maximum lag.
It is sometimes desirable to produce a periodic output signal which is in phase with the center phase orientation of a periodic input signal. One device for accomplishing this objective is a digital phase lock loop. Such a digital phase lock loop is shown in FIG. 1 d will be described below with reference to FIGS. 1 and 2.
A square, periodic signal I/P.sub.1 is supplied to a synchronous phase detector 10. The synchronous phase detector 10 is digital and operates based on a sampling frequency which is of a higher frequency than the frequency of the input signal I/P.sub.1. Also supplied to the synchronous phase detector is a square, jitter-filtered, periodic output signal O/P.sub.1 which has the se frequency as the input signal I/P.sub.1, and has a phase orientation close to the center phase orientation of the input signal. There will generally be a phase difference between the input signal I/P.sub.1 and the output signal O/P.sub.1 which corresponds to the jitter. This jitter may be measured, for example, at corresponding rising edges of the input signal I/P.sub.1 and the output signal O/P.sub.1.
The synchronous phase detector 10 will output a number of successive up pulses on a first up signal U.sub.1 when the input signal I/P.sub.1 leads the output signal O/P.sub.1. The number of up pulses is proportional to the mount of time by which the input signal I/P.sub.1 leads the output signal O/P.sub.1. For example, in FIG. 2, at time T.sub.2, the input signal I/P.sub.1 leads the output signal O/P.sub.1 by 2 counts of the sampling frequency of the synchronous phase detector 10. Therefore, the first up signal U.sub.1 of the synchronous phase detector 10 outputs two successive up pulses.
Similarly, the synchronous phase detector 10 will output a number of down pulses on a first down signal D.sub.1 when the output signal O/P.sub.1 leads the input signal I/P.sub.1. The number of down pulses is proportional to the amount by which the output signal O/P.sub.1 leads the input signal I/P.sub.1. For example, in FIG. 2, at time T.sub.4, the output signal O/P.sub.1 leads the input signal I/P.sub.1 by 1 count of the sampling frequency of the synchronous phase detector 10. Therefore, the first down signal D.sub.1 of the synchronous phase detector 10 outputs one down pulse.
The first up signal U.sub.1 and the first down signal D.sub.1 are supplied to a 4-bit up/down counter 12. The up/down counter 12 will increment (i.e. add one to its count) each time an up pulse is received on the first up signal U.sub.1. For example, in FIG. 2, at time T.sub.2, two up pulses are supplied to the up/down counter 12. Therefore, the up/down counter 12 increments by two, from 1101h to 1111h. Note that numbers followed by an `h` are in binary form. The up/down counter 12 will decrement (i.e. subtract one from its count) each time a down pulse is received on the first down signal D.sub.1. For example, in FIG. 2, at time T.sub.4, one down pulse is supplied to the up/down counter 12. Therefore, the up/down counter 12 decrements by one, from 1111h (shown at time T.sub.4) to 1110h (shown at time T.sub.5).
When the 4-bit up/down counter 12 is at its maximum count, 1111h, and it receives another up pulse, then the up/down counter 12 overflows. In this example, the count of the up/down counter 12 rolls over to 0000h at overflow, and the up/down counter 12 sends out an up pulse on a second up signal U.sub.2. This is shown in FIG. 2, at time T.sub.6. At time T.sub.5, the count of the up/down counter 12 is 1110h. Just before T.sub.6 the up/down counter 12 receives two, successive up pulses. The first of these up pulses causes the up/down counter 12 to increment to 1111h, as explained above. The second of these up pulses causes the counter to overflow and roll over to 0000h. Therefore, a second up pulse (called a correction pulse) is output on the second up signal U.sub.2.
When the 4-bit up/down counter 12 is at its minimum count, 0000h, and it receives another down pulse, then the up/down counter 12 underflows. In this example, the count of the up/down counter 12 rolls to 1111h at underflow, and the up/down counter 12 sends out a down pulse on a second down signal D.sub.2.
The second up signal U.sub.2 and the second down signal D.sub.2 are supplied to a digitally controlled oscillator 14. The digitally controlled oscillator 14 produces the output signal O/P.sub.1. When an up pulse is received on the second up signal U.sub.2, then the digitally controlled oscillator 14 will adjust the phase of the output signal O/P.sub.1 in the leading direction (i.e. it will make the output signal O/P.sub.1 shift to an earlier time). When a down pulse is received on the second down signal D.sub.2, then the digitally controlled oscillator 14 will adjust the phase of the output signal O/P.sub.1 in the direction opposite the leading direction (i.e. it will make the output signal O/P.sub.1 shift to a later time).
The output signal O/P.sub.1 is fed back from the digitally controlled oscillator 14 to synchronous phase detector 10. By this feedback, the up/down counter insures that the output signal O/P.sub.1 follows close to the average center of the jitter on the input signal I/P.sub.1.
However, an input signal may be subject to frequency offset and jitter at the same time. Frequency offset occurs when the frequency of the input signal and output signal drift apart. This often occurs due to slight differences in high frequency sampling clocks used to generate the input and output signals respectively. Frequency offset can causes an increasing phase difference between the input signal and the output signal over time. If frequency offset is not compensated for, then the phase of the output signal will tend to be driven in either the leading or the lagging direction with respect to the input signal.
One example of a periodic signal which is subject to jitter and frequency offset is the 8 kilohertz clock signal which is typically transmitted over telephone lines in conjunction with digital data communication over the telephone lines. These signals are typically subject to jitter of about 1.3 microseconds peak-to-peak amplitude with a jitter frequency down to 1 hertz. It can be helpful to have an 8 kilohertz clock locked to the center of the transmitted 8 kilohertz clock for purposes such as effective detection and modulation/demodulation of digital data communicated over the telephone line in sync with the transmitted 8 kilohertz clock.
If a digital phase lock loop, such as that described above, is used to filter jitter from an input signal, then the output signal may not respond well to account for frequency offset. In fact, there is a risk that frequency offset can cause the input and output signals to become so far out of phase that data communicated in sync with the input signal will be lost when transmitted to components operating based on the output signal of the digital phase lock loop.